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VLSI System Design 6th Sem ECE/EEE/6188/Feb 2021 Diploma Paper

Download Previous Year Diploma Paper of VLSI System Design 6th Sem ECE/EEE/6188/Feb 2021 Diploma Paper

VLSI System Design 6th Sem ECE/EEE/6188/Feb 2021 Diploma Paper

Duration: 1.15Hrs.                                                                 M.Marks:25

                                     SECTION-A

Q2. Attempt any THREE questions.                                                   3×5=15

i. Discuss the features of VHDL.
ii. Write down the VHDL code for half adder circuit.
iii. Write down the difference between concurrent and sequential statement.
iv. Explain the concept of CPLD.
v. Discuss in brief about concurrent statement.
vi. Explain the if-then-elsif conditional statement in VHDL programming.
vii. Write a short note on operator overloading.

                                     SECTION-B

Q3. Attempt any three questions.                                                       3×10=30

  1.  What are the advantages and disadvantages of Optical Fiber Communication.
  2. List the various types of LED’s. Discuss the various types of LED structures.
  3. Describe Optical Power Budgeting ?
  4. What is the need of an Optical Amplifier? Discuss SOA.
  5. Explain the different types of losses in Optical Fibre Communication.
  6. Write short notes on (any two)
  1. Effect of dispersion on data Rate
  2. WDM
  3. Historical perspective of Optical Communication

VLSI System Design 6th Sem ECE/EEE/6188/Feb 2021 Diploma Paper

Get Started https://www.youtube.com/watch?v=y_wJffQkeWo&list=PLA9Q9SDZ781WXNAWit379A4CRLMvjGiUw&index=6&t=0shttps://www.youtube.com/watch?v=mV41CMWonN4&list=PLA9Q9SDZ781WXNAWit379A4CRLMvjGiUw&index=7&t=0shttps://www.youtube.com/watch?v=M_RR6LVICp0&list=PLA9Q9SDZ781WXNAWit379A4CRLMvjGiUw&index=20&t=0shttps://www.youtube.com/watch?v=3BNQLUnbNpYhttps://www.youtube.com/watch?v=ZDkyNOzoG8A&list=PLA9Q9SDZ781WXNAWit379A4CRLMvjGiUw&index=8&t=0shttps://www.youtube.com/watch?v=s0LVPE0Q3LE&list=PLA9Q9SDZ781WXNAWit379A4CRLMvjGiUw&index=14&t=0s

Section B :VLSI System Design 6th Sem ECE/EEE/6188/Feb 2021 Diploma Paper

Discuss the features of VHDL.

Features of VHDL.

Write down the VHDL code for half adder circuit.

VHDL code for half adder circuit.

Write down the difference between concurrent and sequential statement.

Difference between concurrent and sequential statement.

Explain the concept of CPLD.

Concept of CPLD.

Discuss in brief about concurrent statement.

 Concurrent statement.

Explain the if-then-elsif conditional statement in VHDL programming.

 if-then-elsif conditional statement in VHDL programming.

 Write a short note on operator overloading

Short note on operator overloading.

VLSI System Design 6th Sem ECE/EEE/6188/Feb 2021 DiplomaPaper Click Here

VLSI System Design 6th Sem ECE/EEE/6188/Feb 2021 Diploma Paper

Get Started https://www.youtube.com/watch?v=UHX6f8TIvX8https://www.youtube.com/watch?v=M_RR6LVICp0https://www.youtube.com/watch?v=mV41CMWonN4https://www.youtube.com/watch?v=s0LVPE0Q3LE&list=PLA9Q9SDZ781WXNAWit379A4CRLMvjGiUw&index=14&t=0s

Section c :-VLSI System Design 6th Sem ECE/EEE/Feb 2021 Diploma Paper

Design a combinational circuit for 3:8 decoder using VHDL.

Combinational circuit for 3:8 decoder using VHDL.

Explain the different operators used in VHDL.

Different operators used in VHDL.

Explain the different modelling techniques used in VHDL.

Different modelling techniques used in VHDL.

What is delay? Explain various types of delay used in VHDL

Delay and various types of delay used in VHDL.

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